1. Technical Field
The present invention relates to a high voltage junction field effect transistor (high voltage JFET) used in a start-up circuit for starting a switching power supply or the like.
2. Background Art
FIG. 8 is a circuit diagram of a switching power supply device 500. The switching power supply device 500 includes a rectifier 51 constituted of a bridge circuit that rectifies 100V or 200V alternating current, a smoothing capacitor 52 that smoothes the rectified current outputted from the rectifier 51, a control circuit 53 that controls and protects the switching power supply device 500, and a transformer 54 that insulates input and output. The power supply device 500 also has a MOSFET 55 that controls ON and OFF switching of current flowing to a primary side 54a of the transformer 54, and a power supply capacitor 56 that acts as a direct current power supply for a control circuit 53. A secondary side 54b of the transformer 54 has a rectifier diode 57 and an output capacitor 58, and direct current voltage is outputted from output terminals 59.
The control circuit 53 includes a start-up circuit 60, a low voltage shutdown circuit 61, a regulator 62, and a BO comparator 63. The control circuit also includes a transmitter 64, a driver circuit 65, an output amp 66, a latch circuit 67, and a PWM comparator 68.
The start-up circuit 60 supplies current to the power supply capacitor 56 during rise time of the switching power supply device 500 to charge the power supply capacitor 56, and acts as a direct current power supply for the control circuit 53. The low voltage shutdown circuit 61 shuts down the start-up circuit 60 when the voltage of the power supply capacitor 56 falls below a prescribed voltage. The BO comparator 63 functions to detect and monitor input voltage levels inputted to a high voltage input terminal VH through a diode 71 to protect a high voltage JFET 80 (brownout function). The driver circuit 65 controls ON and OFF switching of the MOSFET 55 connected to the primary side 54a of the transformer 54 via the output amp 66. Switching this MOSFET 55 ON and OFF controls voltage on the secondary side 54b of the transformer 54 and outputs a prescribed direct current voltage from the output capacitor 58. Other components constituting this switching power supply device 500 are not directly related to the present invention, and an explanation thereof will be omitted.
FIG. 9 is a circuit diagram of the start-up circuit 60, which forms a part of the control circuit 53 in FIG. 8. The start-up circuit 60 includes the high voltage JFET 70 and a start-up auxiliary circuit 90 (start-up internal circuit), which are start-up elements, and a resistor circuit 92 constituted of input voltage detection resistors. The high voltage JFET 70 has a plurality of sources, and a first JFET unit 70a and a second JFET unit 70b. The start-up auxiliary circuit 90 includes a MOSFET 91, which receives current from the sources of the high voltage JFET 70, and other JFETs and MOSFETs. High voltage is inputted to the drain of the high voltage JFET 70 from the high voltage input terminal VH of the start-up circuit 60, and current is supplied to the power supply capacitor 56 through the high voltage JFET 70 and the start-up auxiliary circuit 90 from the VCC terminal. This power supply capacitor 56 is the power supply for the control circuit 53, and the switching power supply device 500 is started through this start-up circuit 60. Explanations for other circuits are omitted here. The voltage inputted from the high voltage input terminal VH is divided at the resistor circuit 92 for detecting this voltage and then inputted to the BO terminal (brownout terminal). The current inputted from the high voltage input terminal VH flows to the MOSFET 91 of the start-up auxiliary circuit 90 through the high voltage JFET 70 and charges the power supply capacitor 56 through the VCC terminal.
FIGS. 10A and 10B are views of a configuration of a conventional high voltage JFET 70, FIG. 10A is a plan view of main parts thereof, and FIG. 10B is a cross-sectional view of the main parts in FIG. 10A cut along the line A-O. This high voltage JFET 70, which is a start-up element, is constituted of a first JFET 502 part and a second JFET part 503, and includes a p-gate region 72 that is the gate on a p-substrate 71, an n-source region 73 surrounded on three sides by the p-gate region 72, an n-drift region 74 that connects to the n-source region 73, and an n-drain region 75 that connects to the n-drift region 74. The high voltage JFET 70 also includes a p+ gate region 76, which is a p-contact region disposed in the surface layer of the p-gate region 72, an n+ source region 77, which is an n-contact region disposed in the surface layer of the n-source region 73, and an n+ drain region 78, which is an n-contact region disposed in the surface layer of the n-drain region 75. The high voltage JFET 70 also includes a LOCOS oxide film 79 disposed on the n-source region 73, the n-drift region 74, the n-drain region 75, and interposed between the n+ source region 77 and the n+ drain region 78. The high voltage JFET 70 also includes a first interlayer insulating film 81 provided on the LOCOS oxide film 79 and covering this film. The first interlayer insulating film 81 also covers a polysilicon electrode 80 disposed on the LOCOS oxide film 79 and connected to the p+ gate region 76. The high voltage JFET 70 further includes, on the first interlayer insulating film 81, a metal gate electrode wiring line 82 connected to the p+ gate region 76, a metal source electrode 83 connected to the n+ source region 77, and a metal drain electrode 84 connected to the n+ drain region 78. The high voltage JFET 70 further includes a second interlayer insulating film 85 disposed on the first interlayer insulating film 81, a source electrode wiring line 86 disposed on the second interlayer insulating film 85 and connected to the source electrode 83, and a drain electrode wiring line 87 (drain pad electrode/VH terminal) connected to the drain electrode 84.
The drain electrode wiring line 87, the drain electrode 84, the n+ drain region 78, and the n-drain region 75 are arranged in the center of the high voltage JFET 70, and the center of each of these has the same circular shape (each is a concentric circle). The inner edge of the n-drift region 74 contacts the n-drain region 75, and the outer edge contacts the p-gate region 72 and the n-source region 73.
The p-gate region 72 has a circular-shaped periphery, and the inner edge of the p-gate region 72 has recesses and protrusions. The n-source region 3 is disposed so as to enter these recesses, and the end thereof facing the center contacts the n-drift region 74.
Next, the operation of the high voltage JFET 70 will be explained. If a rectified voltage of AC100 is applied to the second drain electrode wiring line 87 (drain pad electrode) of the high voltage JFET 70, for example, then the current flows from the n-drain region 75 in the middle of the high voltage JFET 70 to the start-up auxiliary circuit 90 through the n-source region 73 disposed on the periphery and charges the power supply capacitor 56 through the VCC. The control circuit 53 starts operating when the power supply capacitor 56 has reached a prescribed voltage.
The current following through the high voltage JFET 70 increases the potential (source potential) of the n-source region 73 of the high voltage JFET 70, which causes a pn junction 89 of the n-source region 73 and the p-gate region 72, which is formed so to surround the source, to become reverse biased. This reverse bias causes a depletion region to spread to the n-source region 73 and the n-drift region 74. The depletion region 95 that has spread from the gate region 72, which is on both sides of the n-source region 73, to the n-source region 73 and the n-drift region 74 connects at a pinch-off point P in the n-drift region 74 surrounded by both sides of the p-gate region 72, thereby pinching off the high voltage JFET 70 (causing the JFET 70 to be in a cutoff state). Thus, the potential of the n+ source region 77 changes the spread of the depletion region and the constant current value. If the cut-off voltage is high, current will stop flowing, and the high voltage JFET 70 will turn OFF. Until this cut-off state is completely met, cut-off current flowing through the high voltage JFET 70 will remain at a uniform level and flow from the n+ source layer 77 to a drain D of the JFET 91 in the start-up auxiliary circuit 90 through the first source electrode 83 and the second source electrode wiring line 86.
FIG. 11 is a view that explains a state in which the high voltage JFET 70 has been pinched off. The depletion region 95, which has spread from the p-gate layer 72 to the n-drift layer 74, causes the drain current to be uniform. The depletion region 95 connects when the potential of the n-source region 73 increases, and this pinches off the high voltage JFET 70 and stops the drain current from flowing even if the drain voltage is increased, thereby causing the high voltage JFET 70 to turn OFF. The drain current remains uniform and does not increase. The area where the depletion region 95 has connected is the pinch-off point P. The voltage at the time of pinch-off is called the cutoff voltage Vcut, and the current is called the cutoff current Icut.
The cutoff current Icut initially flows to the power supply capacitor 56 from the VCC terminal. As the power supply capacitor 56 becomes gradually charged, however, the current that is charging the power supply capacitor 56 falls below the cutoff current Icut, and the switching power supply device 500 begins operating when the power supply capacitor 56 has reached a prescribed power supply voltage. At this point, current is supplied from the power supply capacitor 56 to the control circuit 53, and the voltage of the power supply capacitor 56 decreases. To compensate for this decrease, current is supplied to the power supply capacitor 56 from the high voltage input terminal VH through the high voltage JFET 70, the JFET 91, and the VCC terminal, and the power supply capacitor 56 maintains a uniform voltage while the switching power supply device 500 is operating. If the cutoff voltage Icut of the high voltage JFET 70 is low, however, the current supplied to the power supply capacitor 56 decreases, and it becomes impossible to maintain a uniform voltage of the power supply capacitor 56.
When assembling the switching power supply device 500, an ESD (electrostatic discharge) surge is sometimes introduced to the high voltage JFET 70. There are two types of ESD surges: the Human Body Model (HBM±), and the Machine Model (MM±).
In regards to MM− and HBM−, a large parasitic diode formed of the n-source region 73, the n-drift region 74, the n-drain region 75, and the p-substrate 71 becomes forward biased, and the high voltage JFET 70 itself can protect against the negative ESD surge. MM+ is a low voltage of approximately 200V, and thus the high-voltage JFET 70 can also protect against this ESD surge.
HBM+, however, is at least approximately 1000V to 2000V; therefore, it is difficult for the high voltage JFET 70 alone to protect against this ESD surge.
Patent Document 1 discloses a horizontal junction field effect transistor in which the drain is disposed in the center and a large number of sources surround the transistor.
Patent Documents 2 and 3 disclose resistor elements for detecting input voltage being formed in parallel from an input pad electrode, with these resistor elements being arranged in an interlayer insulating film on the drain region.